7 Conclusion

This paper presents a new hardware-software co-design methodology for resource constrained SoC realized in a deep submicron process (DSM). The methodology is useful for multimedia applications optimized for latency. The approach addresses layout and hardware aspects relevant to system design: it considers the dependency of task communication speed on interconnect parasitic, as well as the possibility of sharing coarse and medium grained IP cores across tasks. The methodology includes an original algorithm for bus architecture synthesis. The co-design process performs three successive steps: Using simulated annealing, co-design explores for combined task and communication partitioning and scheduling, and finding feasible requirements for the minimum speed of communication links. Exploration employs Performance Models (PM) to express relationships between system performance (latency and communication speed flexibility), specification attributes, and design decisions. The second step synthesizes and routes the bus architecture. IP cores are placed using a hierarchical cluster growth algorithm. Next, bus architecture synthesis finds a set of possible building blocks (using the PBS bitwise generation algorithm), and assembles them together using simulated annealing. The paper presents a special table structure, named bus architecture synthesis table, and select-eliminate method to prune low quality bus architectures. The third step reschedules tasks and communications using precise information on bus speed for the best found bus architecture. The co-design methodology improves the practicality of system-level design for DSM technologies. The bus synthesis algorithm creates customized bus architectures in a short time depending on the data communication needs of the application, and the required performance. Layout information is important in deciding the bus architecture topology. Experiments showed that it is impractical to postulate a unique bus architecture as the best, as there is little re-using among bus architectures optimized for different constraints. Experiments also indicated that PM are more effective than well known synthesis metrics, like task priorities. For SA-based exploration using PM, system latency was up to 20% shorter than for list scheduling. Reason was that PM avoid the modeling limitations of priority functions. PM are general, flexible, and can be easily extended for new design activities without requiring cumbersome validation. The combined partitioning and scheduling technique offers latency improvements of up to 40% as compared to a method, which separates partitioning and scheduling. For highly parallel applications, sharing of medium and coarse grained resources improves latency by up to 30% as compared to sharing of coarse grained cores only.